The present invention relates to a semiconductor memory device, and more particularly to improvement in read operation speed from a memory core (hereinafter called a "memory cell array") and that in read operation margin.
A portion of conventional semiconductor memory devices incorporates a local sense amplifier provided for each column and a global sense amplifier provided for a peripheral circuit region. FIG. 1 shows an example of a read-out circuit of a semiconductor memory device of the foregoing type.
The read-out circuit shown in FIG. 1 incorporates a memory cell array 1; a plurality of bit lines 2; column select means 3 constituted by transistor switches connected to the plural bit lines 2; local sense amplifiers 4 connected to the column select means 3; a sense line 5 disposed along a side of the memory cell array 1; a connecting line 6 between the sense line 5 and the peripheral circuit region; a global sense amplifier 7 formed in the peripheral circuit region; and an output circuit 8 for producing output of a read data signal.
As described later, the connecting line 6 for establishing the connection with the peripheral circuit region forms a portion of the sense line 5. The sense line 5 and connecting line 6 form a bus line. Therefore, the sense line 5 and the connecting line 6 for establishing the connection with the peripheral circuit region are collectively called sense lines 5 and 6.
Similarly, also data lines for transferring write data to the memory cell array 1 incorporates a first write control circuit provided in the peripheral circuit region forming the global sense amplifier 7. Moreover, a second write control circuit is provided for each region in which the local sense amplifiers 4 is formed. Thus, write data is written on the memory cell array 1 through the first and second write control circuits and the data lines (corresponding to the sense lines 5 and 6 shown in FIG. 1). To cause a problem experienced with the conventional technique to easily be understood, a path for transferring write data to the memory cell array 1 is omitted in FIG. 1.
A read operation of the conventional semiconductor memory device shown in FIG. 1 will now be described. A case will be described in which each bit line 2 is composed of a bit line pair composed of two bit lines for transferring complementary read data signals. A slight potential difference read from the memory cell appears on the bit line pair. The potential difference is amplified by the local sense amplifiers 4 connected to the bit line pair.
In FIG. 1, each of the column select means 3 connected to the bit lines 2 and the sense lines 5 and 6 is drawn symbolically as one line. When the complementary signals are processed, each line indicates a pair of lines.
The local sense amplifiers 4 are connected to the bit lines 2 through the column select means 3 and disposed along the side of the memory cell array 1. The read data signal from the memory cell and amplified by the local sense amplifiers 4 is transferred to the complementary sense line 5 disposed along the side of the memory cell array 1 and the complementary connecting line 6 (hereinafter called a "sense line pair 5 and 6) with the peripheral circuit region. Then, the read data signal is amplified by the global sense amplifier 7 disposed in the peripheral circuit region so as to be output from the output circuit 8 for the read data signal.
The signals which appear on the sense line pair 5 and 6 are distinct from the signals having a voltage amplitude in a usual complementary logic circuit. Each signal has a voltage amplitude having an intermediate voltage level as compared with the power supply voltage similarly to the read data signal from the bit line pair. The logic of the foregoing signal is determined in accordance with the positive or negative polarity of the potential difference which appears on the sense line pair 5 and 6.
The reason why the read data signal having the intermediate voltage level which is lower than the power supply voltage is transferred, will now be described.
As described above, the sense line pair 5 is the signal line extending along the side of the memory cell array 1. Therefore, the largest length of the sense line pair 5 is the length of one side of the memory cell array 1.
Since a multiplicity of the local sense amplifiers 4 are connected in parallel, parasitic capacitance C which is added to the sense line pair 5 is a considerably large value. Therefore, delay time caused from R*C product which is defined by the resistance R and the parasitic capacitance C of the sense line pair 5 is a very large value as compared with that of another signal line.
When the signal lines having the considerably large R*C product are used to transfer the signals each having the voltage amplitude for the usual complementary logic circuit, power dissipation caused from charge/discharge of the parasitic capacitance is enlarged. Thus, reduction in the read operation speed caused from the R*C delay cannot be prevented.
Therefore, also the read data signals from the sense line pair 5 and 6 are the signals having the intermediate voltage level having the relatively small voltage similarly to the bit line pair. Moreover, the global sense amplifier 7 connected to the sense line pair 6 is used to convert the read data signal into the signal having the voltage amplitude for the usual complementary logic circuit. Thus, the power dissipation can be suppressed, causing the read speed to be raised.
The structure has been described in which the local sense amplifiers 4 are each connected to the respective bit lines 2. When the number of the columns is enlarged to correspond to the trend for high capacities of the semiconductor memory devices, the local sense amplifiers 4 are each connected for several columns through a column select means 3 constituted by transistor switches.
When the number of the columns is small, a method is sometimes employed with which the local sense amplifiers 4 are not formed and the potential difference of the bit line pair read from the memory cell is directly transferred to the sense line pair 5 and 6 through the column select means 3. In either case, the read data signal having the relatively low intermediate voltage level is transferred in the sense line pair 5 and 6.
Referring to FIG. 2A, the relationship among the levels of the read data signals will now be described which is realized when three adjacent pairs A and /A, B and /B and C and /C are extracted from a plurality of the sense line pairs 5 to transfer the read data signals. As described above, the sense line pair 5 extends along the one side of the memory cell array 1. Therefore, the parasitic capacitance of the signal line constituting the sense line pair 5 is enlarged. Also a capacitive coupling caused from an interline parasitic capacitance between adjacent signal lines is enlarged.
Therefore, the voltage level of the complementary read data signals which are transferred through the sense line 5 is changed according to the degree of the capacitive coupling between adjacent signal lines. Since each of the complementary read data signals is transferred as a relatively low intermediate voltage level, the change in the difference in the voltage level between the complementary read data signals caused from the capacitive coupling critically obstructs normal data transfer. As a matter of course, the change in the difference in the voltage level of the complementary read data signals caused from the capacitive coupling is a problem common to the sense line pair 5 and the sense line pair 6 for the connection.
Referring to FIG. 2A, the foregoing problem will furthermore specifically be described. An assumption is made that either of the sense line pair 5 or 6 which encounters the potential difference caused from the complementary read data signals and which has a higher voltage level is "H", and the residual pair having a lower voltage level is "L". Moreover, an assumption is made that when data is "1", the sense lines A, B and C are made to be "H", and the sense lines /A, /B and /C are made to be "L". When data is "0", the sense lines A, B and C are made to be "L", and the lines /A, /B and /C are made to be "H". Note that the sense line pair 5 and 6 is drawn as a straight bus line to simplify the illustration in FIG. 2A.
As a matter of course, the polarities of "H" and "L" of the difference in the voltage level between the sense lines constituting the sense line pair 5 and 6 are always reverse because the read data signals are complementary signals. The relationship between the voltage levels between the sense lines /A and B and /B and C belonging to the adjacent sense line pair 5 and 6 is determined depending on the species of data of the complementary read data signals which are transferred to the corresponding sense line pair 5 and 6, that is, whether data is "1" or "0".
When the read data signal "1" is transferred to the sense line pairs A and /A and C and /C and the read data signal "0" is transferred to the sense line pair B and /B as shown in FIG. 2A, the voltage change at the same level takes place between /A and B and between /B and C. Thus, the capacitive coupling between the sense lines mutually assists the voltage change to accelerate the voltage change.
When the read data signal "1" is transferred to all of the sense line pairs as shown in FIG. 2B, voltage change in the reverse direction takes place between the sense lines /A and B and between the sense lines /B and C. That is, the capacitive coupling mutually obstructs the voltage change. Therefore, the level difference of the complementary input signals to the global sense amplifier 7 is reduced. Thus, there arises a problem in that the read operation margin is reduced and also the read operation speed is reduced.
In a bus line layout in which a plurality of sense line pairs are disposed in parallel as shown in FIGS. 2A and 2B, no adjacent signal line is disposed on the outside of the sense line pair disposed at the edge of the bus line layout. Therefore, the state of the operation of the sense line pair at the edge of the bus line layout is different from that of the operation in the bus line layout.
As one of methods of preventing the problem of the capacitive coupling, the same wiring layer which is the same as each sense line is used to dispose a dummy signal line between each of the sense line pairs A and /A, B and /B and C and /C as shown in FIG. 3. Moreover, the voltage level of the dummy signal line is fixed to a predetermined value (for example, the ground level). Thus, a shield line G is disposed between the sense line pairs.
In the foregoing case, one shield line G must be provided for two sense lines forming one pair. Therefore, the occupation area of the bus line constituted by the sense line pair is considerably enlarged. An assumption is made that the diameter of the shield line G is the same as that of the sense line in, for example, the read operation. The provision of the shield line G enlarges the chip area required for wiring the sense line to 1.5 time.
A high-speed SRAM (Static Random Access Memory) having a large bit width must use bus line constituted by a multiplicity of thick signal lines. Therefore, when a multiplicity of the shield lines G are formed in the bus line, the chip area of the semiconductor memory device is considerably enlarged.
As another method of preventing the influence of the capacitive coupling between the adjacent sense lines, a method of twisting the sense line pair as shown in FIG. 4A is known. When the adjacent sense lines forming one pair are interchanged mutually at predetermined intervals as indicated with the vertical dashed lines shown in FIG. 4A, the influence of the capacitive coupling can be compensated.
To sufficiently compensate the capacitive coupling, the number of twists must be enlarged. A sense line wired for a long distance on which a great influence of the R*C delay is exerted has a structure that the connection to different wired layers is repeated through a multiplicity of contact holes 10 for forming twists as shown in FIG. 4B. Therefore, the parasitic resistance is raised and unbalance of the capacity is enlarged, thus causing a problem to arise in that the operation margin is reduced.
As described above with reference to FIG. 1, the local sense amplifiers 4 for driving the sense line pair 5 and 6 are dispersed when the local sense amplifiers 4 are connected to the sense line pair 5. Therefore, the read performance encounters dependency on the position.
When, for example, the local sense amplifier 4 is connected to an intermediate point of either side of the twisted sense line or the column select means 3 is directly connected to the same as shown in FIG. 4C, the capacity from the connection point to the global sense amplifier becomes unbalance. Hence it follows that the capacity of the twisted sense line becomes unbalance. Thus, the read characteristic encounters dependence on the position.
The sense line pair for reading stored information has been described. The data line for transferring write data to the memory cell array suffers from a similar problem. Thus, raising of the operation speed of the semiconductor memory device having a large capacity and enlargement of the operation margin have been inhibited.
As described above, the conventional semiconductor memory device suffers from a problem in that a great influence of the capacitive coupling of the signal line for use to read stored data and write data is exerted. Thus, the write speed and the operation margin are reduced.